Reductions in the size and inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the metal-oxide-semiconductor (MOS) device and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor. In addition, junction depths of MOS devices are reduced accordingly.
When the scales of integrated circuits are reduced to 65 nm and below, further reduction of the gate lengths and junction depths becomes increasingly difficult. This is partially because of the diffusion of impurities during annealing processes. Particularly for PMOS devices, lightly-doped source/drain (LDD) regions and source/drain regions comprises p-type impurities such as boron or BF2. Due to the high diffusibility of boron and BF2, impurities easily diffuse-out from originally implanted regions during subsequent annealing steps. In addition, the implantation process has the drawback of having boundaries with a slowly changing impurity concentration, and thus it is difficult to implant impurities only into the desired regions. As a result, the junction depth is further enlarged.
Accordingly, a new method for forming MOS devices with improved short channel characteristics is needed.